1. Technical Field
The present disclosure relates to a method of fabricating an integrated circuit comprising an interconnection structure, and to an integrated circuit fabricated by this method.
2. Description of the Related Art
Interconnection structures comprise conductive lines and conductive vias connecting the conductive lines and traversing a dielectric material. Aluminum or copper are conventionally used to form conductive lines and vias. Copper is increasingly replacing aluminum due to its better resistance to electromigration and higher conductivity, allowing for smaller conductive lines and vias and lower power consumption.
FIGS. 1A to 1C are cross-sectional views of an integrated circuit showing different steps of fabricating a conventional interconnection structure I1. In FIG. 1A the interconnection structure I1 comprises, from bottom to top, a base L0, an etch stop layer S0, a first dielectric layer D1, an etch stop layer S1, a second dielectric layer D2, and a mask layer M2.
The integrated circuit also comprises a conductive line F1 (shown in lateral cross-section) and a conductive line F1′ (shown in longitudinal cross-section) made of a first conductive material C1, embedded in the dielectric layer D1, and surrounded on the bottoms and sides by diffusion barriers B1, B1′. At the step shown in FIG. 1A, two patterned openings P2, P2′ have been made in the mask layer M2. The patterned openings P2, P2′ have a misalignment error E1 (shown from center of desired location to center of actual location) with respect to lines F1, F1′, such as due to photolithographic limitations.
During steps shown in FIG. 1B, two holes H2, H2′ are made in the dielectric layer D2, through the openings P2, P2′ of the mask M2. Typically, the dielectric material D2 is first etched (shown as arrows) using a first chemical reagent until the etch stop layer S1 is reached, then a second chemical reagent is used to etch the etch stop layer S1 to reach the underlying conductive lines F1, F1′. An “overetch” step is often performed to ensure that no residue remains on the top surfaces of the conductive lines. Due to the misalignment error E1, the underlying dielectric layer D1 to the side of the conductive line F1 is also etched while the conductive lines are being overetched, causing a lateral etch region E2 in the dielectric material.
During steps shown in FIG. 1C, diffusion barriers B2, B2′ are deposited on the sidewalls and bottoms of holes H2, H2′. Due to the deep depth and small size of the lateral etch region E2, a thin or non-existent diffusion barrier B2″ is deposited on the walls of the lateral etch region E2. The barriers B2, B2′, B2″ are then generally covered with a “seed layer” of a conductive material (not shown), and then the holes H2, H2′ are filled with a conductive material C2 to form conductive vias F2, F2′ in electrical contact with lines F1, F1′ at contacts N1, N1′. Barrier B2″ may further cause a poor adherence of the “seed layer” in the lateral etch region E2, which leads to a poor-filling of the conductive material C2 in the lateral etch region E2, creating a void E3. Furthermore, barrier B2″ allows conductive material to diffuse from via F2 into the dielectric material D1, such that line-to-line leakage may occur, causing a time-dependent dielectric breakdown (TDDB) test failure.
In addition, a critical distance CD between lines F1, F1′ is not met due to the lateral etch region E2. As a result, an electrical field between lines F1, F1′ may increase, also with an increased possibility of breakdown. Additionally, contact N1 between line F1 and via F2 is smaller than desired, causing higher local current density, which may lead to an increased rate of electromigration and an earlier formation of another void, such that line F1 will no longer be connected to via F2.
It may be desired therefore to provide an alternate method for manufacturing an integrated circuit comprising an interconnection structure.